1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to a semiconductor memory device having a data transfer path.
2. Description of the Related Art
In general, a semiconductor memory device includes a plurality of memory banks, each of which is composed of plural memory cells.
The semiconductor memory device is designed to provide a plurality of data bandwidths to operate. For example, a semiconductor memory device, which supports both of an X8 mode and an X16 mode and has 16 input/output (I/O) pads, performs a data I/O operation with the 16 I/O pads when the data bandwidth option is set to an X16 mode while utilizing 8 of the 16 I/O pads when the data bandwidth option is set to an X8 mode.
For example, the semiconductor device having two memory banks, each of which corresponds to 8 I/O pads, selects all of two memory banks and performs the data I/O operation with both of the memory banks at the same time during the X16 mode while selecting one of the two memory banks and performing the data I/O operation with the selected memory bank during the X8 mode.
A multi-purpose register (MPR) provides information storage for additional operation such as a training operation. The MPR stores a predefined data pattern, for example, a training data with a preset data pattern. During a MPR mode, the MPR outputs the preset data for a specific operational purpose, irrespective of normal read and write operation to data stored on memory cells. With the MPR, it is possible to perform a tuning operation for guaranteeing a high-speed operation between a semiconductor system and a memory chip.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes first to fourth banks 10 to 40, first to fourth global lines GIO_UR[63:0], GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0], a MPR 50 first and second data I/O units 60 and 70, first and second repeaters 80 and 90, first and second data pads DQ[0:7] and DQ[8:15].
The first to fourth banks 10 to 40 receive/output a normal data through the first to fourth global lines GIO_UR[63:0], GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0], respectively. The MPR 50 loads a training data having a predetermined data pattern on the first and second global fine GIO_UR[63:0] and GIO_DR[63:0] in a training mode.
The first data I/O unit 60 transfers data between the first data pads DQ[0:7] and the first to fourth global lines GIO_UR[63:0], GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0], irrespective of a bandwidth option. The second data I/O unit 70, which is enabled according to the bandwidth option, transfers data between the second data pads DQ[8:15l ] and the third and fourth global lines GIO_UL[63:0] and GIO_DL[63:0].
The first repeater 80 transfers data loaded on the first global line GIO_UR[63:0] to the third global line GIO_UL[63:0] according to the bandwidth option in the training mode. The second repeater 90 transfers data loaded on the second global line GIO_DR[63:0] to the fourth global line GIO_DL[63:0] according to the bandwidth option in the training mode.
For example, the first data pads DQ[0:7] and the first to fourth global lines GIO_UR[63:0], GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0] work irrespective of the bandwidth option of the 8 I/O mode and the 16 I/O mode while the second data pads DQ[8:15] and the third and fourth global lines GIO_UL[63:0] and GIO_DL[63:0] work according to the bandwidth option of the 16 I/O mode. The first and second repeater 80 and 90 work during the training mode.
The conventional semiconductor memory device has a concern as follows.
In the training mode, the training data stored in the MPR 50 are loaded on the first global line GIO_UR[63:0] and the second global line GIO_DR[63:0].
In the X8 mode, the first data output unit 62 outputs the training data loaded on one of the first global line GIO_UR[63:0] and the second global line GIO_DR[63:0] to the first data pads DQ[0:7].
In the X16 mode, the first repeater 80 forwards the training data loaded on the first global line GIO_UR[63:0] to the third global line GIO_UL[63:0]. Also, the second repeater 90 forwards the training data loaded on the second global line GIO_DR[63:0] to the fourth global line GIO_DL[63:0]. Then, the first data output unit 62 and the second data output unit 72 output the training data loaded on the first to fourth global lines GIO_UR[63:0], GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0] to the first data pads DQ[0:7] and the second data pads DQ[8:15], respectively.
In a normal mode and the X8 mode, the first data I/O unit 60 forwards a normal data between the first data pads DQ[0:7] and the first to fourth global lines GIO_UR[63:0] GIO_DR[63:0], GIO_UL[63:0] and GIO_DL[63:0].
In the normal mode and the X16 mode, the first data I/O unit 60 forwards the normal data between the first data pads DQ[0:7] and the first and second global lines GIO_UR[63:0] and GIO_DR[63:0], Also, the second data I/O unit 70 forwards the normal data between the second data pads DQ[8:15] and the third and fourth global lines GIO_UL[63:0] and GIO_DL[63:0].
Different from the training mode, the first and second repeaters 80 and 90 are not involved in data transfer in the normal mode. Since each of the global lines is composed of 64 lines, each of which has a relatively long length, the first and second repeaters 80 and 90 when utilized solely for the training mode have a relatively large drivability, which is a burden of semiconductor design in view of size of the semiconductor device.